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This Month in PLCT: Issue 37 (September 1, 2022)


At the PLCT lab and the TAISIER team, we had a busy August preparing and hosting the second RISC-V Summit in China. Due to the ongoing pandemic, we have decided to hold the summit remotely, with over 12 sessions held concurrently in different cities in China. We would like to thank everyone for making this year’s summit our largest one yet and a successful example for concurrent sessions in different local venues.

Last month also saw significant growth in our TAISIER. We grew our roster to 20 full-time staff members, began work on a RISC-V port for a distro named OpenAnolis, awarded title to our first LV4 intern, and commenced work with our BJ67 operating system observation project with over 8 interns.

In September, the PLCT lab will experiment with building an > 1,024-node RISC-V cluster. We look forward to working with you in this new project.

V8 for RISC-V

General updates.

OpenJDK for RV32GC (Shi Ningning [史宁宁])

  1. Fix some reg num problems
  2. clean the code in sharedRuntime_riscv32.cpp
  3. rewrite the long_move()
  4. Fix the bug of regname
  5. change the relationship between j_rargx and c_rargx
  6. Fix the instructions offset in vtableStubs_riscv32.cpp
  7. Fix the instructs in
    • Fix the subL_reg_reg
    • Fix the mulL()
    • Fix the loadConL
    • Fix the divL/modL
    • Fix the storeL and storeimmL0
    • Fix loadConD0
    • Fix the storeLConditional
    • Fix the compareAndSwapL
    • Fix the compareAndSwapLAcq()
    • Fix the compareAndExchangeL
    • Fix the compareAndExchangeLAcq
    • Fix the weakCompareAndSwapL
    • Fix the weakCompareAndSwapLAcq
    • Fix the get_and_setI/F
    • Fix the get_and_setIAcq/setLAcq
  8. Improve the div system
  9. Improve the code style of loadUS2L
  10. Improve the xchg system
  11. Improve the atomic_add system
  1. JDK mainline regression testing on SiFive Unmatched.
    • Tier 1-3 tests clean.
    • Need more testing for Tier 4.
  2. Pull requests merged into mainline:
    • (8291952: riscv: Remove PRAGMA_NONNULL_IGNORED)
    • (8292338: aarch64: Use cbnz instruction in gen_continuation_enter when possible)
    • (8293050: RISC-V: Remove redundant non-null assertions about macro-assembler)
  3. Pull requests approved/under review for mainline:
    • (8291893: riscv: remove fence.i used in user space)
    • (8291947: riscv: fail to build after JDK-8290840)
    • (8292407: Improve Weak CAS VarHandle/Unsafe tests resilience under spurious failures)
    • (8292713: Unsafe.allocateInstance should be intrinsified without UseUnalignedAccesses)
    • (8292867: RISC-V: Simplify weak CAS return value handling)
    • (8293007: riscv: failed to build after JDK-8290025)
    • (8292575: riscv: Represent Registers as values)
    • (8293011: riscv: Duplicated stubs to interpreter for static calls)
    • (8293065: Zero build failure on AArch64 and RISCV64 after JDK-8293007)
    • (8293035: Cleanup MacroAssembler::movoop code patching logic aarch64 riscv)
  4. JBS issues reported:
    • (test/hotspot/jtreg/gc/shenandoah/compiler/ timeouts after JDK-8292285)
  5. Sponsored pull requests to mainline:
    • (8292187: aarch64: Remove duplicate header files)
    • (8293011: riscv: Duplicated stubs to interpreter for static calls)
  6. Commits for the RV64 Loom port:
    • (riscv: Implement TemplateInterpreterGenerator::generate_Continuation_doYield_entry)
    • (riscv: Implement gen_continuation_enter)
    • (riscv: Implement continuation_enter_setup, fill_continuation_entry and continuation_enter_cleanup)
    • (Remove check_emit_size parameter from MacroAssembler::trampoline_call)
    • (Add new parameter check_emit_size for MacroAssembler::trampoline_call)
    • (Implement NativePostCallNop and NativeDeoptInstruction for riscv)
    • (Implement SmallRegisterMap for riscv)
    • (Implement stackChunkOopDesc::relativize_frame_pd and stackChunkOopDesc::derelativize_frame_pd for riscv)
    • (Implement LIRGenerator::do_continuation_doYield for riscv)
    • (Small refactoring for AbstractInterpreter::layout_activation)
  7. GHA support for RISC-V (based on Ubuntu 22.04):
    • (8283929: GHA: Add RISC-V build config)

OpenJDK Upstreaming (Zhang Dingli [张定立])

OpenJDK Upstreaming (Cao Gui [曹贵])

OpenJDK8 Backporting (Zhang Xiang [章翔])

  1. Build support.
    • Build routine,
  2. Build fixes.

Clang/LLVM for RISC-V



Note: Further testing pending.

GNU Toolchain for RISC-V


Arch Linux for RISC-V

Gentoo for RISC-V

Nixpkgs for RISC-V

Firefox (SpiderMonkey) on RV64GCV

With help from the V8 work group.

DynamoRIO RV64GC Enablement

Preliminary support for RV64GC implemented in DynamoRIO, which will now build on RV64GC (no additional feature supported).

Current five-stage road map for DyanmoRIO’s RV64GC support:

  1. Introduce RISC-V platform-specific functions, frameworks, definitions, etc., allowing DynamoRIO to build on RISC-V. (Done)
  2. Setup RISC-V CI for automated compilation and testing. (In Progress)
  3. Refine RISC-V platform-specific functions and definitions, make DynamoRIO’s built-in example tools functional.
  4. Refine RISC-V unit- and feature-tests, setup CI for automated testing and instruments for long-term maintenance.
  5. Continue RISC-V feature enablement for more complex programs, prepare for long-term maintenance.

See for a more detailed to-do list.

OpenCV for RV64GCV

As part of our GSoC 2022 project, we are currently implementing a new Universal Intrinsic backend for RVV (RISC-V Vector), making the existing Universal Intrinsic framework compatible with scalable (variable-length) backends.

Previously, we have already finished implementing the aforementioned changes to the Universal Intrinsic framework. In August, we have implemented all platform-specific Universal Intrinsic functions and introduced respective unit tests and submitted relevant patches to upstream:

As a result, the new Universal Intrinsic backend for RVV not only supports variable register lengths, it also improves performance significantly over the original backend design, which had an issue where it generated redundant Load/Store instructions. As a next step, we plan to optimize hot-spot functions OpenCV’s image processing module and acquire RVV-enabled devices for performance testing.

For more details on this project:

Experimental SIMD in LIBCXX

LuaJIT RV64G porting

Our intern has unfortunated resigned. We are currently in search for a new intern.




Other Support for RISC-V International

Please stay tuned.


Please stay tuned.

OpenArkCompiler Community

Shi Ninging (史宁宁) continues to work on compiling the OpenArkCompiler Weekly, which received the 128th edition.

You may find new weekly editions of the OpenArkCompiler Weekly on Sundays on…


Please stay tuned.

Upstream RVV Dialect Proposal

Google’s IREE partner Diego proposed an RFC for a generic Vector Masking Representation in MLIR,


OSPP Mentorship

Buddy Compiler



New features:


New features:

Chisel / FIRRTL (CAAT Work Group)

coreboot for riscv

Please stay tuned.



Submitted various patches to upstream.


The Aya Theorem Prover

👉View current pull requests here👈

You may find the full list of August changes here.

RISC-V Platform Evaluation


  1. Created a frontend for RVLab’s hardware management platform using Vue.js.
    • Learning to make of Vue.js’ parent and child component functionalities - using value passing and function calls in various dialog interfaces.
    • Completed device distribution, device editing, relay listing, new/delete relays, and delete device pages in the hardware management interface.
    • Completed user management, user roles, role listing, new/delete roles, delete user pages.
    • Completed the User Profile interface, as well as a functional Change Password page.
    • Successfully deployed the RVLab hardware management platform locally on a Ubuntu 22.04 system using Dockerfile and docker compose. This platform will be deployed for production in a virtual machine. Due to the fact that the MQTT server was deployed in the RVLab’s internal network, the virtual machine will require both Internet and intranet access.
    • Revised Flask backend code to adapt to the Vue frontend.
  2. RVLab infrastructure provisioning.
    • Installed the latest Debian image on one Unmatched board.

openEuler for RISC-V

See TAISIER’s bi-weekly reports,

Debian for RISC-V

Now published in a bi-weekly format, please find these reports at the debian-riscv mailing list.