This is our tech blog in English. Chinese version is PLCT-Weekly.
If you have questions or sugguests, feel free to open an issue.
This is the way of how to compile and checkout the scalar cryptography extension with toolchain, which is the sub ISA of RISC-V.
Xinyi Li, 2021.1.12
This is the roadmap of the PLCT Lab in 2021, which is about our 2021 plan in the direction of RISC-V development tool.
Wei Wu, 2020.11.30
The PLCT Lab is inviting everyone inside the RISC-V community to write to us the dev-tools or orther softwares you wish to have in the RISC-V ecosystem. Feel free to open an issue or PR and describe the tools you want.
Chen Wang, 2020.11.24
After a period of hard work, we can now run an Android “minimal system” on QEMU of RISC-V.
The blog is a brief summary of the current work. Although the road ahead is still long, there is something to have a look.
Dingli Zhang, 2020.11.20
BishengJDK 11 now brings the template interpreter and backends of C1/C2 compiler to the RISC-V world. We supports RV64G (G used to be represent the IMAFD base and extensions of RISC-V ISA) with BV (bit-manipulation and vector extensions) on the way, and the compressed instructions are out of plan.
This test is to build the JDK on RISCV64 and start to do some benchmark on HiFive Unleashed.
Yin Zhang, 2020.11.16
This is a Google Summer of Code project participated by Yin, a graduate student of PLCT lab. We adds a back-end implementation based on RISC-V vector extension for OpenCV in this project. This blog introduced the project and how to build and use it.
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